Ultra large scale integrated circuit (ULSI) memory devices require increased capacitance per unit area to allow small storage cell capacitors, to achieve high charge storage for soft error prevention, and to operate at 1.5 volts. Such capacitors must also meet stringent reliability considerations. Desirable properties of gate oxides include high dielectric constant for high capacitance, low electrical conductance, and high dielectric breakdown voltage.
Currently, there is great interest in oxides with high dielectric constants such as Ta205 for application as gate oxides in ULSI DRAMs and SRAMs. Recent publications have reported that the dielectric quality of Ta205 is greatly improved by high temperature annealing. In particular, annealing at up to 900.degree. C. reduces the leakage current density to the 1E-12 range, with a major reduction (approximately 5000 times) occurring for temperatures between 800.degree. C. and 900.degree. C.
Annealing Ta205 at temperatures up to 900.degree. is also beneficial in reducing the leakage current because the annealed film crystallizes into Beta-Ta205 and the defect density decreases such that hopping conductivity is reduced. For sufficiently high anneal temperature, i.e. 800.degree.-900.degree. C., hopping is substantially eliminated and Fowler-Nordheim tunneling at the top electrode (farthest away from the device substrate) of a capacitor structure in the storage device controls conduction through the oxide. An interfacial layer exists at the silicon-Ta205 boundary, and this transition layer is assumed to be leaky because it contains TaSi.sub.2.
The silicon transition layer has a negative effect on dielectric capacitance because of its low dielectric constant, which gives the effective transition-oxide sandwich a lower dielectric constant. For annealing above 800.degree. C., the transition region grows in thickness, causing a six fold decrease in capacitance at 900.degree. C. Because of this limitation, the optimum anneal temperature for Ta205 is about 850.degree. C. because higher temperatures give lower leakage but also lower capacitance.